Texas Instruments Integrates Copper with Low-k Material to Reduce Both Resistance and Capacitance
Dallas (December 4, 1997) -- For the first time anywhere, researchers at Texas Instruments have demonstrated the successful combination of copper wiring with a microporous insulating material called xerogel in an integrated circuit. This breakthrough approach to manufacturing chips could lead to future digital signal processors (DSP) and microprocessors that are at least 10 times faster and use much less power than today's most powerful chips.
The successful coupling of the two technologies, each new and radical in its own right, allows electrical signals to flow more freely throughout a chip reducing troublesome electrical resistance and capacitance effects.
The prototype chips built by researchers at TI's Kilby Center offer a solution to one of the semiconductor industry's most important looming problems. As semiconductor manufacturers create more powerful chips by shrinking and packing more transistors and other circuit elements onto them, the manufacturing processes become increasingly complex. For the next generation of chips, these devices will be so small and so close together that the wiring which connects the transistors, known as interconnect, will impede the free flow of electrical signals throughout the chip, thereby capping its overall performance. Electrical resistance and capacitance in the interconnect are the main culprits.
TI's new process technology using copper and xerogel will offer the highest performance alternative to those processes recently announced. Unlike previously disclosed interconnect technology using copper rather than aluminum for circuit wiring, the TI demonstration goes one step further by embedding the lower resistance copper in an insulating material which provides vastly improved electrical isolation.
The prototype chips built by TI lowered electrical resistance by approximately one-third as compared with a traditional aluminum/oxide-interconnect system. In addition, the process integrated into the TI chips also provided approximately one-third the capacitance of conventional interconnects with equivalent resistance, resulting in a potential 10X improvement in IC performance.
TI researchers built the new interconnects in a damascene architecture, in which wires were, in effect, inlaid into 0.3-micron wide trenches formed in a composite xerogel/oxide dielectric stack. The trenches were patterned using phase-shifted photolithography and reactive ion etching, and then lined with a titanium nitride diffusion barrier layer to prevent the copper from penetrating the dielectric and underlying silicon substrate. Following barrier metal deposition, a thin copper "seed" layer was deposited to facilitate the subsequent electroplating process used to completely fill the trenches. The inlaid copper leads were then isolated by removing unwanted copper using chemical-mechanical polishing of the surface.
Interconnect currently is made from aluminum, which has a relatively high electrical resistance compared with copper and is more prone to electromigration, or movement of metal atoms during current flow. The latter effect can shorten the life of integrated circuits, which are typically expected to operate for 10-20 years without exhibiting any performance degradation.
Although copper has much better conductivity and reliability than aluminum, it readily diffuses through oxide and into the silicon from which chips are made, rendering them useless. Thus, the semiconductor industry has been cautious in the implementation of copper interconnects until special materials and processes could be developed to prevent contamination.
TI has also done considerable research in the area of novel dielectric materials which provide lower interconnect capacitance. Capacitance impedes the flow of electrical signals more perniciously than resistance by sapping signal strength through cross-coupling to adjacent leads. While capacitors are used extensively in computer memory devices such as DRAMs (Dynamic Random Access Memories), the capacitance between the closely spaced metal leads utilized for circuit wiring is often detrimental to overall performance. Capacitance effects also increase power dissipation and lead to interference or crosstalk between adjacent metal leads that can limit transistor operating voltage. Both of these effects are of particular concern for portable computer devices such as digital phones and notebook computers.
In future chips, capacitance problems will worsen as wires only about 1000 angstroms apart (atomic-scale distances) will run alongside each other through these dielectric layers. Rerouting the wires or increasing the spacing is not an option because chips will be densely packed with transistors. The solution to this capacitance crisis lies in increasing the insulating property of the dielectric material. Air is considered the perfect insulator. It has a dielectric constant or "k" of 1, the measure of its insulating value. But it is impossible to use air as an insulator in chips because it has no mechanical structure or rigidity. Commonly used silicon dioxide (SiO2) has dielectric constant of 4.2 as compared with a k of 3.0 - 2.5 for the Hydrogen-Silsesquioxane (HSQ) low-k dielectric in production at TI.
Xerogel may be the ultimate dielectric material for chips, not only because it has an ultra-low dielectric constant of less than 2.0, but because its inherent insulating properties can be varied depending upon process manufacturability requirements. Xerogel is a highly porous material with billions of microscopic nanopores or bubbles that contain air. It can be made from a number of substances, including familiar SiO2. Xerogel made from SiO2 features excellent thermal stability and mechanical rigidity.
TI researchers will present more details about their work on Wednesday, December 10 at the IEEE International Electron Devices Meeting (IEDM) in Washington, DC. The IEDM is one of the world's leading semiconductor technology conferences.