SynaptiCAD

Welcome to SynaptiCAD, your source for cutting edge timing analysis and VHDL & Verilog generation and simulation software! We currently offer five products:

TestBencher Pro: a VHDL/Verilog test bench generator that creates bus-functional HDL models from timing diagrams.

VeriLogger Pro: Verilog simulator with waveform viewer, debugging environment, and hierarchical browser.

DataSheet Pro: documentation environment for managing large projects, features OLE, style-sheets, views, vector and web image creation, and supports all major publishing programs.

WaveFormer Pro: an interactive HDL simulator. Design information changes cause automatic updates to simulation results providing instant feedback on the impact to system functionality and performance.

Timing Diagrammer Pro: the industry's most advanced timing diagram editor with support for TDML, FrameMaker MIF files, MS Word metafiles, EPS, & more.

Download a Free Demo from www.syncad.com